1. Field of the Invention
The present invention relates to a synchronous momory device using a clock signal. More particularly, it relates to a synchronous memory device which has a plurality of clock input buffers in order to separately control a clock input buffer simultaneously controlling both a data output buffer and a latch circuit by using one command signal.
2. Description of the Prior Art
FIG. 1 depicts a block diagram of a conventional semiconductor memory device using a clock input buffer.
As shown in FIG. 1, the conventional memory device having a clock input buffer includes: a clock input buffer 10 for buffering an input clock signal; a buffering portion 20 for increasing a driving ability of an output signal of the clock input buffer 10; an output enable signal generator 30 which receives an output signal CLKT4 of the buffering portion 20, and generates an enable signal of a data output buffer 40; a data output buffer 40 which buffers a data and then generates the data to an output pad DQ PAD; an input signal buffer 50 which buffers predetermined input signals (i.e., AN, /RAS, /CAS, /WE, . . . ); a delay circuit 60 for delaying an output signal of the input signal buffer 50 during a predetermined time; and a latch circuit 70 for latching an output signal of the delay circuit 60 by the output signal CLKT4 of the buffering portion 20.
Operations of the semiconductor device will now be described below.
The signal CLKT4 generated from the clock input buffer 10 and the buffering portion 20 can control the data output buffer 40 and the latch circuit 70 at the same time. That is, the signal CLKT4 is input to the output enable signal generator 30. The output enable signal generator 30 enables the data output buffer 40, the data output pad DQ PAD outputs the data. Also, while the signal CLKT4 is applied to the output enable signal generator 30, the signal CLKT4 is applied to the latch circuit 70 and thus controls a stored latch signal.
FIG. 2 depicts a differential amplifier used as a data input buffer shown in FIG. 1. Since the circuit shown in FIG. 2 is well known to those skilled in the art, its operation is omitted below.
FIG. 3 depicts an example of the latch circuit shown in FIG. 1.
As shown in FIG. 3, if the control signal CLKT4 is activated as a high level, the control signal CLKT4 latches a value of an input signal before an electric potential of the input signal is changed.
If an input signal INOUT is at a high level, an input signal INOUTB is to be a low level. Accordingly, n-channel metal oxide semiconductor (hereinafter referred to as NMOS) transistor MN6 is turned on greater than NMOS transistor MN7. As a result, a NMOS transistor MN4 and a p-channel metal oxide semiconductor (hereinafter referred to as PMOS) transistor MP5 are turned on, so that an output terminal LATOUT outputs a high signal and an output terminal LATOUTB outputs a low signal. In addition, PMOS transistors MP3 and MP6 controlled by the control signal CLKT4 maintain signals applied to the output terminals.
As described above, in the conventional semiconductor memory device having a clock input buffer, the control signal CLKT4 is applied to the latch circuit 70 simultaneously with being applied to the data output buffer 40. Accordingly, a current driving size of the buffering portion 20 for driving the control signal CLKT4 should be increased, and the size of the clock input buffer 10 should be also increased. In particular, controlling the data output buffer 40 is an important path to determine a clock access time which is the most important element in a SDRAM field. If there are much current consumption in the clock input buffer 10, the access time becomes increased.